Can you please provide me the BSNL JTO to SDE Competitive Exam Question paper as I am doing the preparation of this exam so I need this to know about the exam pattern and the scheme of exam of BSNL JTO to SDE Competitive Exam so please provide me this?

As you are asking for BSNL JTO Sample papers so on your demand I am providing same for you :

1. For reflection co-efficient |r| = 1/2 VSWR is

(A) 2

(B) 3 (Ans)

(C) C

(D) 8



2. Radiation resistance of a half wave dipole is

(A) 73 ? (Ans)

(B) 377 ?

(C) 300 ?

(D) 50 ?



3. Which of the following is not Maxwell's equation ?

(A) B = ?H

(B) E = D/?

(C) E = J/?

(D) E = ?D (Ans)



4. A medium is called isotropic when

(A) ? is zero

(B) ? is a scalar constant (Ans)

(C) ? = ?

(D) ? = ??



5. Which of the following is not a wide band antenna

(A) marconi (Ans)

(B) helical

(C) rhombic

(D) folded dipole



6. The wave which "lies down and dies" is called

(A) ground wave (Ans)

(B) sky wave

(C) space wave

(D) spherical wave



7. When cathode is positive with respect to anode in an SCR, the number of p-n junction is

(A) 1

(B) 2 (Ans)

(C) 3

(D) 4



8. The impulse response and the excitation function of a linar time invariant causal system are shown in Fig. (a) and (b) respectively. The output of system at t = 2 sec is equal to





(A) 0

(B) 1/2 (Ans)

(C) 3/2

(D) 2

Solution : y (y) = f x (t) h (t - t) dt




Out Put = 1/2 * 2 1/2 = 1/2



9. The initial contents of the 4-bit serial-in-parallel-out right-shift, Shift Register shown in Fig.is 0110. After three clock pulses are applied, the contents of the Shift Register will be




(A) 0000

(B) 0101

(C) 1010 (Ans)

(D) 1111

Solution : 4-bit SIPO

1 XOR (1, 0) = 1 1011

2 XOR (1, 1) = 0 0101

3 XOR (0, 1) = 1 1010

contents will be 1010.



10. Fig. shows the circuit of a gate in the Resistor Transistor Logic (RTL) family. The circuit represents a




(A) NAND

(B) AND

(C) NOR

(D) OR (Ans)



Vi1 Vi2 Vx V0 Q1 Q2 Q3

L L H L OFF OFF ON

L H L H OFF ON OFF

H L L H ON OFF OFF

H H L H ON ON OFF

The circuit represent an OR. Hence choice is d.



11. The logic realized by the circuit shown in Fig.




(A) F = A . C

(B) F = A + C (Ans)

(C) F = B . C

(D) F = B + C





F = does not depend on B.

F = A C + A C = A ? C



12. A Lissajous pattern, as shown in Fig below, is observed on the screen of a CRO when voltage of frequencies fx and fy are applied to the x and y plates respectively. fx : fy is then equal to


(A) 3 : 2

(B) 1 : 2 (Ans)

(C) 2 : 3

(D) 2 : 1

Solution : fx/ff = Points of tangency to vertical line/Points of tangency to horizontal line = 1/2

or fx : fy = 1 : 2



13. In the transistor circuit shown in Fig. below, collector-to-ground voltage is + 20 V. Which of the following is the probable cause of error ?


(A) Collector-emitter terminals shorted

(B) Emitter to ground connection open (Ans)

(C) 10 k ? resistor open

(D) collector-base terminals shorted