Hi buddy here I am looking for syllabus/notes of VTU Electronic Circuits & Logic Design Laboratory 10CSL38a paper , so can any one provide me ??

As you are looking for syllabus/notes of VTU Electronic Circuits & Logic Design Laboratory 10CSL38a paper , so on your demand here I am providing same for you

Electronic Circuits & Logic Design Laboratory
(Common to CSE & ISE)

Subject Code:10CSL38 IA

Part A
1. a. Design and construct a suitable circuit and demonstrate the working of positive clipper,double ended clipper and positive clamper using diodes.b. Demonstrate the working of the above circuits using a simulation package

2. a. Design and construct a suitable circuit and determine the frequency response, inputImpedance, output impedance and bandwidth of a CE amplifier.b. Design and build the CE amplifier circuit using a simulation package and determinethe voltage gain for two different values of supply voltage and for two different valuesof emitter resistance

.3. a. Design and construct a suitable circuit and determine the drain characteristics andtransconductance characteristics of an enhancement mode MOSFET.b. Design and build CMOS inverter using a simulation package and verify its truth table.

4. a. Design and construct a Schmitt trigger circuit using op-amp for the given UTPand LTP values and demonstrate its working.b. Design and implement a Schmitt trigger using Op-Amp using a simulation packagefor two sets of UTP and LTP values and demonstrate its working.

5. a. Design and construct a rectangular waveform generator (op-amp relaxationOscillator) for a given frequency and demonstrate its working..b. Design and implement a rectangular waveform generator (Op-Amp relaxationOscillator) using simulation package and demonstrate the changes in frequency whenall resistor values are doubled.

6. Design and implement an Astable Multivibrator using 555 Timer for a given frequencyand duty cycle.
Part B

7. a. Given a four variable expression, simplify using Entered Variable Map (EVM) andrealize the simplified logic using 8:1 MUX.b. Design and develop the verilog/VHDL code for 8:1 MUX. Simulate and verify itsworking.

8. a. Realize a J-K Master/Slave FF using NAND gates and verify its truth table.b. Design and develop the verilog/VHDL code for DFF with positive edge triggering.Simulate and verify its working.

9. a. Design and implement a mod n (a<8) synchronous up counter using JK FF IC’s anddemonstrate its working. b. Design and develop the verilog/VHDL code for mod 8 up counter simulate and verifyits working.

10 a. Design and implement ring counter using 4-bit shift register and demonstrate itsworking.b. Design and develop the verilog /VHDL code for switched tail counter. Simulate andverify its working.

11 Design and implement asynchronous counter using decade counter IC to count up from0 to n (n≤9) and demonstrate its working.12 Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and1Department of Computer Science and Engineering