The syllabus of M. Tech (VLSI Design) program as offered by Gandhi Institute of Technology and Management or GITAM University is as follows:

M. Tech (VLSI Design) I Semester
Digital System Design
Course Code: EPRVD101 Credits: 4 Hours: 4 per week
Category: Core

UNIT I
Review of Logic Design Fundamentals: Combinational Logic / Boolean Algebra and Algebraic Simplification Karnaugh Maps / Designing with NAND and NOR Gates / Hazards in Combinational Circuits / Flip-Flops and Latches / Mealy Sequential Circuit Design / Design of a Moore Sequential Circuit / Equivalent States and
Reduction of State Tables / Sequential Circuit Timing / Tristate Logic and Busses

UNIT II
Introduction to VHDL: Computer-Aided Design / Hardware Description Languages / VHDL Description of Combinational Circuits / VHDL Modules / Sequential Statements and VHDL Processes / Modeling Flip-Flops Using VHDL Processes / Processes Using Wait Statements / Two Types of VHDL Delays: Transport and Inertial Delays / Compilation, Simulation, and Synthesis of VHDL Code / VHDL Data Types and Operators / Simple Synthesis Examples / VHDL Models for Multiplexers / VHDL Libraries / Modeling Registers and Counters Using
VHDL Processes / Behavioral and Structural VHDL / Variables, Signals, and Constants / Arrays / Loops in VHDL / Assert and Report Statements

UNIT III
Introduction to Programmable Logic Devices: Brief Overview of Programmable Logic Devices / Simple Programmable Logic Devices (SPLDs) / Complex Programmable Logic Devices (CPLDs) / Field-Programmable Gate Arrays (FPGAs) Design Examples: BCD to 7-Segment Display Decoder / A BCD Adder / 32-Bit Adders / Traffic Light Controller / State Graphs for Control Circuits / Scoreboard and Controller / Synchronization and Debouncing / A Shift-and-Add Multiplier / Array Multiplier / A Signed Integer/Fraction Multiplier / Keypad Scanner / Binary Dividers

UNIT IV
SM Charts and Microprogramming: State Machine Charts / Derivation of SM Charts / realization of SM Charts/ Implementation of the Dice Game / Microprogramming / Linked State Machines

UNIT V
Designing with Field Programmable Gate Arrays: Implementing Functions in FPGAs / Implementing Functions Using Shannon’s Decomposition / Carry Chains in FPGAs / Cascade Chains in FPGAs / Examples of Logic Blocks in Commercial FPGAs / Dedicated Memory in FPGAs / Dedicated Multipliers in FPGAs / Cost of
Programmability / FPGAs and One-Hot State Assignment / FPGA Capacity: Maximum Gates Versus Usable Gates / Design Translation (Synthesis) / Mapping, Placement, and Routing

Attached Files

GITAM University M. Tech (VLSI Design) Syllabus.pdf (279.5 KB, 161 views)