ATS 2015 is the twenty fourth in this arrangement of symposia began in 1992 committed to testing, issue tolerant processing and the configuration of solid circuits and frameworks. ATS is perceived as the headliner in Asia that covers the numerous measurements of testing and adaptation to non-critical failure.

The symposium concentrates on the key test will emerge because of the capacity to outline complex frameworks, for example, robots that incorporate sensors, correspondence frameworks, processors, transducers and empowering programming. Notwithstanding finishing post-produce test methods, such frameworks and pertinent gadgets must show adaptation to non-critical failure and survivability attributes.

Some of the Selected Papers for ATS are as follows:

Test Generation
1. Malav Shah, Industry Talk (Texas Instruments, India): Lowering Test Costs in Low Cost Microcontrollers
2. Masahiro Fujita: Detection of test patterns with unreachable states through efficient invariant identification
3. Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara: A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation
4. Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang and Laung-Terng Wang: SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

Power Aware Testing
1. Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim and Sungho Kang: Scan Chain Reordering-aware X-Filling and Stitching for Scan Shift Power Reduction
2. Zhou Jiang, Dong Xiang and Kele Shen: A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test
3. Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki and Toshinori Hosokawa: A Don’t Care Filling Method to Reduce Capture Power based on Correlation of FF Transitions

Memory Test and Repair
1. Shyue-Kung Lu and Masaki Hashizume: Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories
2. Josef Kinseher, Leonardo Zordan and Ilia Polian: On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs
3. Che-Wei Chou, Yong-Xiao Chen and Jin-Fu Li: Testing Inter-Word Coupling Fautls of WideIO DRAMs

New DFT Approaches
1. Jyotirmoy Saikia, Industry Talk (Synopsys India): Designing Efficient Multi-Codec Scan Compression
2. Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki and Chen Wang: TestExpress – New Time-Effective Scan-Based Deterministic Test Paradigm
3. Satyadev Ahlawat, Jaynarayan Tudu, Anzhela Matrosova, and Virendra Singh: A New Scan Flip-Flop Design to Eliminate Performance Penalty of Scan

Timing and Delay Test
1. Xijiang Lin, Wu-Tung Cheng and Janusz Rajski: On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults
2. Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich and Jun Qian: Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
3. Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael Kochte, Eric Schneider and Hans-Joachim Wunderlich: Optimized Selection of Frequencies for Faster-Than-at-Speed Test
4. Ankush Srivastava, Virendra Singh, Adit D Singh and Kewal K Saluja: A Methodology for Identifying High Timing Variability Paths in Complex Designs

Testing in FINFET and Emerging Technologies
1. Loganathan Lingappan, Industry Talk (Intel USA): Need for online test generation/manipulation/profiling at advanced process nodes
2. Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Chien-Mo Li and Cheng-Sheng Pan: Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
3. Joyati Mondal, Debesh Kumar Das and Bhargab B. Bhattacharya: Design-for-Testability in Reversible Logic Circuits based on Bit-Swapping
4. Ashwin Chintaluri, Abhinav Parihar, Arijit Raychowdhury, Helia Naeimi and Suriyaprakash Natarajan: A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

Design Analysis, Verification and Validation
1. Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno and Kunihiro Asada: A Technique for Analyzing On-chip Power Supply Impedance
2. Payman Behnam and Bijan Alizade: In-circuit Mutation-based Automatic Correction of Certain Design Errors
3. Raphael Viera, Rodrigo Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale and Bruno Rouzeyre: Validation Of Single BBICS Architecture In Detecting Multiple Faults
4. Saikat Dutta, Soumi Chattopadhyay, Ansuman Banerjee and Pallab Dasgupta: A new approach for minimal environment construction for modular property verification

Circuits for Security and Resilience
1.Dooyoung Kim, Muhammad Adil Ansari, Jihun Jung and Sungju Park: SCAN-PUF: PUF Elements Selection Methods for Viable IC Identification
2. Sabyasachi Deyati, Barry Muldrey, Adit Singh and Abhijit Chatterjee: Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security
3. Adithyalal P M, Shankar Balachandran and Virendra Singh: A Soft Error Resilient Low Leakage SRAM Cell Design
4. Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi and Masahiko Yoshimoto: Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path

Test for Diagnosis
1. Tino Flenker, André Sülflow and Görschwin Fey: Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation
2. Srinivasa Shashank Nuthakki and Santanu Chattopadhyay: An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets
3. Michael Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omana, Cecilia Metra and Hans-Joachim Wunderlich: Intermittent and Transient Fault Diagnosis on Sparse Code Signatures

Testing 3D Structures
1. Rajit Karmakar, Aditya Agarwal and Santanu Chattopadhyay: Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs Under Resource and Power Constraints
2. Konstantin Shibin, Vivek Chickermane, Brion Keller, Christos Papameletis and Erik Jan Marinissen: At-speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic
3. Jun Zhou, Huawei Li, Tiancheng Wang, Ying Wang and Xiaowei Li: TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs

Resilient System Design and Test
1. Sukrat Gupta, Neel Gala, G. S. Madhusudan Desikan and Kamakoti Veezhinathan: SHAKTI-F: A Fault Tolerant Microprocessor Architecture
2. Guopei Liu, Ying Wang, Huawei Li and Xiaowei Li: A Lightweight Timing Channel Protection for Shared Memory Controllers
3. Swagata Mandal, Suman Sau, Amlan Chakrabarti, Sushanta Pal and Subhasish Chattopadhyay: FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code
4. V Prasanth, Rubin Parekhji and Amrutur Bharadwaj: Improved Methods for Accurate Safety Analysis of Real-life Systems