Ok, here I am providing you the notes of Logic Design of B.Tech CSE III Semester of Visvesvaraya Technological University VTU.

VTU B.Tech CSE III Sem Logic Design notes

Subject Code: 10CS33
I.A. Marks : 25
Hours/Week : 04
Exam Hours: 03
Total Hours : 52
Exam Marks: 100

PART-A

UNIT – 1 7 Hours
Digital Principles, Digital Logic: Definitions for Digital Signals, Digital Waveforms, Digital Logic, 7400 TTL
Series, TTL Parameters The Basic Gates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive and
Negative Logic, Introduction to HDL.

UNIT – 2 6 Hours
Combinational Logic Circuits
Sum-of-Products Method, Truth Table to Karnaugh Map, Pairs Quads, and Octets, Karnaugh Simplifications,
Don’t-care Conditions, Product-of-sums Method, Product-of-sums simplifications, Simplification by Quine-
McClusky Method, Hazards and Hazard Covers, HDL Implementation Models.

UNIT – 3 6 Hours
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, Encoders, Exclusive-or Gates, Parity
Generators and Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL
Implementation of Data Processing Circuits

UNIT – 4 7 Hours
Clocks, Flip-Flops: Clock Waveforms, TTL Clock, Schmitt Trigger, Clocked D FLIP-FLOP, Edge-triggered D
FLIP-FLOP, Edge-triggered JK FLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact
Bounce Circuits, Various Representation of FLIP-FLOPs, Analysis of Sequential Circuits, HDL Implementation of
FLIP-FLOP

PART-B

UNIT – 5 6 Hours
Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In - Serial Out, Parallel In -
Parallel Out, Universal Shift Register, Applications of Shift Registers, Register Implementation in HDL

UNIT – 6 7 Hours
Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus,
Decade Counters, Presettable Counters, Counter Design as a Synthesis problem, A Digital Clock, Counter Design
using HDL

UNIT – 7 7 Hours
Design of Synchronous and Asynchronous Sequential Circuits: Design of Synchronous Sequential Circuit:
Model Selection, State Transition Diagram, State Synthesis Table, Design Equations and Circuit Diagram,
Implementation using Read Only Memory, Algorithmic State Machine, State Reduction Technique.
Asynchronous Sequential Circuit: Analysis of Asynchronous Sequential Circuit, Problems with Asynchronous
Sequential Circuits, Design of Asynchronous Sequential Circuit, FSM Implementation in HDL

UNIT – 8 6 Hours
D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A
Accuracy and Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous
A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution

Text Book:
1. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 7th Edition,
Tata McGraw Hill, 2010

For complete notes here is the attachment



Contact-

Visvesvaraya Technological University Karnataka
Jnana Sangama, VTU Main Road, Machhe, Belagavi, Karnataka 590018
0831 249 8196

Attached Files

VTU B.Tech CSE III Sem Logic Design notes.pdf (2.98 MB, 190 views)