The specifications for the FPGA based Modem IP Core and Development Kit required by DRDO is as given below:

Name of Item / Features
High Data Rate Modulator IP Core:
Multi-Project VHDL & C (site-based, full-capability) Qty: 01
With following features

1. Digital Modulation Support for BPSK, QPSK, offset-QPSK (OQPSK), 8PSK
2. Data Rate – continuous variable 2.5 kbaud to 25 Mbaud
3. Input Data FIFO
4. Symbol Mapper
5. Integrated matched filter with programmable alpha
6. Sample Interpolation upto a factor of 8192 in internal filter
7. Integrated transmit symbol rate NCO
8. 14-bit DAC I & Q interfaces, Built- in sin( x) / x DAC compensation filters
9. Synchronous design with single clock
10. Configurable via the 32-bit microprocessor interface
11. Data Input interface: IP (Internet Protocol)
12. Deliverables

Enhanced High Data Rate Demodulator IP Core
Multi-Project VHDL & C (site-based, full-capability) Qty: 01
With following features
1. Digital Demodulation Support for BPSK, QPSK, offset-QPSK (OQPSK), 8PSK
2. Data Rate – continuous variable 4.9kbaud to 25 Mbaud
3. Decimation upto a factor of 4096 in internal filter
4. N-stage symbol rate blind adaptive equalizer, support time spread upto 0.2 microsec
5. Integrated matched filter with programmable alpha
6. 10 to 14-bit ADC I & Q interface resolution
7. Radio Interface to eliminate DC offsets and IQ imbalances
8. Fast Acquisition Algorithms
9. Independent acquisition and track parameters
10. Configurable timing and carrier lock characteristics
11. Constellation output interface suitable for soft-decision FEC
12. AGC control interface to analog front end
13. Synchronous design with single clock
14. Configurable via the 32-bit microprocessor interface
15. Software Driver in C
16. Data Output interface: IP (Internet Protocol)
17. Deliverables

Modem IP Cores Evaluation Platform Qty: 05
With following features
1. Xilinx Virtex-4 FPGA engine or higher (deployment of items 1(a) and 1(b) together in same
FPGA should not consume more than 40 % of processing resource. Remaining should be available for user application)
2. Dual 12-bit 170Ms/s ADCs or higher
3. Dual 16-bit 500Ms/s oversampling single-ended DACs or higher
4. Dual variable gain amplifiers
5. Low-noise onboard clocks
6. IF Interface – 70 MHz
7. External clock input option
8. Ethernet connectivity via L2 Interface
9. On-board FPGA FLASH
10. On-board power supply conditioning
11. Baseband expansion port
12. Deliverables