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July 4th, 2014 03:47 PM
Rohit Barla
Re: WIPRO WASE past year question papers free download

As you want to get the WIPRO WASE past year question papers so here is the information of the same for you:

Some content of the file has been given here:

Q 1) Consider a machine with a byte addressable main memory of 216 bytes and block size of 16 bytes. Assume that a direct mapped cache consisting of 16 lines used with this machine.
A) Show how you would interpret a main memory address to determine its possible location in cache.
B) Suppose the byte with address 1101 1110 0101 1101 is stored in the cache, What are the addresses of all other bytes which can be stored at this particular cache location?
C) How many total bytes of memory can be stored in the cache?
D) Into what line would bytes with each of the following address be stored? (Express answer in Binary or Hex)
1101 1110 0101 1101
1001 0110 0110 1010
1100 0101 0101 1001 (3+3+1+3=10)
Q 2) A) What is an interrupt?
B) Assume that a computer is executing a program and suddenly receives an interrupt signal. Detail the sequence of steps, with words and relevant diagrams, that occur as the interrupt is serviced, and control returned back to the main program. (2+8)
Q 3) A) In a two level memory heirarchy, if the first level has an access time of 20 ns and the second level has an access time of 200ns, what is the hit rate in the first level required to give an average access time of 40 ns? (5)
B) Typically processors will have a signal called Wait for Memory Function Complete (MFC) after a read or write to/from the memory. Why is this signal needed? (5)
Q 4) A) Write the difference between arithmetic shift and logical shift with the help of example for the bit pattern 10011110, shift by 1 unit. Show both Left shift and right shift operations. . (1 * 4=4)
B) Evaluate the following expression using three and two address machine format
X= (A+B X C)/ (D-EX F) (3 * 2=6)
Q5) A) Explain clearly the observations and thinking which led to the birth of the RISC machine. . (3)
B) During a context switch, one has to save the machine state. Saving a large number of registers should lengthen context switch times. Explain therefore how having a large register file actually helps (some) RISC processors speed up context switch times. (4)
C) Explain briefly what is pipelining. Explain what characteristics of RISC make it so suitable for pipelining. (3)
Q6) A) A particular pipelined processor has nine stages and instructions are issued at a rate of one per clock cycle. Ignore penalties due to branch instructions. Total number of instructions is 15. Calculate the speedup of this processor for this Program compared to a nonpipelined processor. (2)
B) What is a superscalar processor? (2)
C) Your ALU can add its two input registers, and it can logically complement the bits of either input register, but it cannot subtract. Numbers are to be stored in two’s complement representation.
i) How would you write a program to do subtraction on this processor? (2)
ii) You now want to implement the subtraction operation as a single instruction. List the micro-operations your control unit must perform to cause subtraction. . (2)
D) Consider a control unit having control memory which is 24 bits wide. The control portion of the microinstruction format is divided into two fields. A microoperation field of 13 bits specifies the micro-operations to be performed. An address selection field specifies a condition, based on flags that will cause a microoperation branch. There are eight flags.
i) How many bits are in the address selection field? (1)
ii) How many bits are in the address field? (1)


Q1. Write an 8086 Assembly language to add two arrays stored at LOCA & LOCB and to store the resultant array in LOCR. (Program - 6 + comments - 4).

Q2. Differentiate between the following:
i) Minimum mode operation and maximum mode operation
ii) Isolated I/O and memory mapped I/O. (5+5)

Q3. Consider a floating point format with 7-bits for the biased exponent and 24 bits for the significand. Show the bit pattern for the following numbers in this format:
a) -720
b) 0.645 (Format 4 + representation 3 X 2)

Q4.a) Design a 64K memory by using 8K chips. Show the complete memory organization. (5).
b) Using the Hamming algorithm, determine the coded word to be transferred if the message is 1011. Assume even parity is used. (5)

Q5. A particular processor has five stages of pipelining – FI (Fetch Instruction), DI (Decode Instruction), FO (fetch Operands), EI (Execute Instruction) and WO (Write Output). Depict the pipeline for the 6 arithmetic instructions. Also draw the timing diagram for the pipeline operation. (5 for Pipeline depiction + 5 for Timing Diagram)

Q6.a) Compare RISC and CISC processors. (5)
b) What are the advantages and Disadvantages of microprogrammed control unit over hardwired control unit. (5)


For more detailed information I am uploading a PDF file which is free to download:
July 4th, 2014 08:28 AM
Unregistered
WIPRO WASE past year question papers free download

Will you please give me the WIPRO WASE past year question papers as it is very urgent for me?

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