The previous year Digital Electronics and Logic Design question paper of S. E. (Computer and I.T) Examination - 2013 of University of Pune is as follows:

SECTION-I
Q1.
a) With the help of Quine-McCluskey method, determine the prime implicants for the following equation:
F (A, B, C, D) = ∑ (0,1,2,5,6,7)
b) Convert the following decimal numbers into their equivalent hexadecimal numbers and octal numbers.
(1) 936 (2) 1507 (3) 23.56 (4) 1.025 (5) 100.5

OR

Q2.
a) Minimize the following functions and realize using minimum number of logic gates.
𝐹1 = ∑𝑚(0,3,5,6,9,10,12,15)
𝐹2 = ∑𝑚(0,1,2,3,11,12,14)
b) Convert the following hexadecimal numbers into their equivalent octal numbers and binary numbers.
(1)A72E (2) BD6.7 (3) 0.AF54 (4) DF (5) FF

Q3.
a) Explain the standard TTL characteristics in detail
b) Draw and explain the working of 2-input CMOS NOR gate.

OR

Q4.
a) Why is it necessary to interface between TTL and CMOS? Draw and explain the circuit arrangement of interfacing CMOS gate to number of TTL gates.
b) Explain with the help of circuit diagram 2-input TTL NAND gate with
Totem Pole output driver

Q5.
a) Design and implement BCD to Excess-3 code converter using dual 4:1 multiplexers and some logic gates.
b) Design 8-bit comparator using IC-7485

OR

Q6.
a) Design and implement BCD to Excess-3 code converter using required logic gates. Show truth table K-maps and circuit diagram of your design
b) Draw and explain 4-bit BCD subtractor using IC 7483. Explain the operation on BCD numbers: 5-7.


Digital Electronics and Logic Design question paper of S. E. (Computer and I.T) University of Pune

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