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Old June 25th, 2016, 04:44 PM
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Default VHDL Viva Questions

Hello sir, I am Yash. I have to give a Viva on VHDL in my college. Can you provide me with some VHDL questions? Please help me.

As you have asked for the VHDL Viva questions, I am providing you with it, check below for the details

Question -1: Write a simple VHDL program for D Flipflop and D latch.
Question -2: Write a VHDL program for 4X1 MUX(Multiplexer).
Question -3: Write a VHDL code for 8 to 3 encoder.
Question -4: Write VHDL program for 4 bit binary counter(up or down).
Question -5: Explain FPGA internal Architecture.
Question -6: Write Verilog program for 1 bit and 4 bit comparators.
Question -7: Write Verilog code for half adder and full adder logic circuit.

Question -8: Explain difference between signal and variable in VHDL.
Answer -8: Signals are used as interconnects between components and also to store temporary values.
Signals can be declared internal to architecture and are not available external to the architecture.
Variable is like other programming language, It is an object whose value may be changed after creation.

Question -9: Explain difference between VHDL and Verilog.
Answer -9: Both are used as language to develop code targetted for FPGA device.
Syntax in Verilog programming is like C language. VHDL syntax are different.

Question -10: How do you implement multiply and divide operation with power of 2 in VHDL or Verilog
Answer -10: Left shift is equivalent to multiply operation and right shift is equivalent to divide operation.
Hence using shift operations the same can be easily and efficiently implemented.

Last edited by Neelurk; April 24th, 2020 at 11:38 AM.
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