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Old June 29th, 2016, 09:01 AM
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Default VTU LD Lab Viva Questions

I am student of Visvesvaraya Technological University (VTU) and from here doing my engineering degree doing Viva exam preparation. Will you please provide me some VTU LD (Logic Design) Lab Viva Questions which was generally asked by university viva exam?

Visvesvaraya Technological University (VTU) is a collegiate public state university in Karnataka State, India.

As per your request below I am providing you the VTU LD Lab Viva Questions:

LOGIC DESIGN (LD) VIVA VOCE QUESTIONS:

1. Explain meaning of implies, subsumes, Implicants, prime implicants.
2. What do you mean by prime implicants and irreduntant conjugate expression/
3. Explain how MEV map differs from K-map?
4. Define half adder and full adder.
5. Define half subtractor and full subtractor.
6. Draw and explain the block diagram of n-bit parallel adder.
7. What do you mean bby carry propagation delay.
8. Explain the method used for carry look ahead generation.
9. Explain the working of n-bit full subtractor with the help of neat block diagram.
10. What is 1's and 2's complement?
11. What is the difference between 1's and 2's complement?
12. What do you mean by comparator?
13. What is decoder?
14. What is encoder?
15. What is priority encoder, and what is the difference between encoder and priority encoder?
16. What is the difference between decoder and encoder?
17. What is multiplexer?
18. Give the applications of mux?
19. What is the difference between decoder and multiplexer?
20. What do you mean by sequential circuits?
21. Give the comparison between combinational and sequential circuits.
22. Give the comparison between synchronous and asynchronous circuits.
23. Draw and explain the working of basic bistable element.
24. What do you mean by latches and flip-flops?
25. Give the difference between latches and flip-flops.
26. Draw and explain the working of a) SR latch b) gated SR latch c) Gated D latch.
27. Explain any one application of SR latch.
28. Draw and explain the working of all flip-flops.
29. What is race around condition? How it is avoided?
30. What is shift register?
31. Explain the 4-bit serial in and serial out shift register.
32. What is serial in parallel out shift register. Explain.
33. State various applications of shift registers.
34. What is jhonson's counter. Explain same for 4-bit.
35. Explain ring counter.
36. What is counter?
37. What is ring counter?
38. Explain the working of 4-bit asynchronous counter.
39. What advantage and disadvantages of counters/
40. What is the difference between synchronous and asynchronous counters?
41. Draw and explain the working of $-bit UP/DOWN synchronous counter.
42. Draw and explain the block diagram of Moore model and Melay model.
43. compare Moore and Melay models.
44. Take the questions for IC number for all the Gates.

Address:
Visvesvaraya Technological University (VTU)
Jnana Sangama, VTU Main Road, Machhe
Belagavi, Karnataka 590018
Phone: 0831 249 8196

Last edited by Neelurk; May 22nd, 2020 at 12:32 PM.
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